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Limits of SiC MOSFETs' Parameter Deviations for Safe Parallel Operation

Title data

Bertelshofer, Teresa ; März, Andreas ; Bakran, Mark-M.:
Limits of SiC MOSFETs' Parameter Deviations for Safe Parallel Operation.
2018
Event: 20th European Conference on Power Electronics an Applications , 17-21 Sept. 2018 , Riga, Lettland.
(Conference item: Conference , Paper )

Abstract in another language

This paper presents a numerical method combined with a device simulation model used to analyse the
parallel connection of several SiC MOSFET dies. Parallel connection is necessary to achieve the desired
current carrying capability of main inverters for xEV-drives. With this method, the effect of asymmetries
within the chips’ on-state resistance coupled with asymmetries in the threshold voltage is investigated.
The investigation result quantifies, to what extent the threshold voltage and the on-state resistance of the
chips can vary at the same time, when the output power of the inverter should only be derated by 5% at
most and no single chip in the inverter should be overheated. To achieve this derating limit, the impact of
the positive temperature coefficient (PTC) of the output characteristic and the thermal coupling between
the paralleled chips is examined.

Further data

Item Type: Conference item (Paper)
Refereed: Yes
Institutions of the University: Faculties > Faculty of Engineering Science > Chair Mechatronics > Chair Mechatronics - Univ.-Prof. Dr.-Ing. Mark-M. Bakran
Profile Fields > Advanced Fields > Advanced Materials
Profile Fields > Emerging Fields > Energy Research and Energy Technology
Research Institutions > Research Units > ZET - Zentrum für Energietechnik
Result of work at the UBT: Yes
DDC Subjects: 600 Technology, medicine, applied sciences > 620 Engineering
Date Deposited: 21 May 2019 05:59
Last Modified: 21 May 2019 05:59
URI: https://eref.uni-bayreuth.de/id/eprint/49040