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Memory Analysis and Performance Modeling for HPC Applications on Embedded Hardware via Instruction Accurate Simulation

Title data

Ditter, Alexander ; Schönwetter, Dominik ; Kuzmin, Anton ; Fey, Dietmar ; Aizinger, Vadym:
Memory Analysis and Performance Modeling for HPC Applications on Embedded Hardware via Instruction Accurate Simulation.
In: Janech, Jan ; Kostolny, Jozef ; Gratkowski, Tomasz (ed.): Proceedings of the 2015 Federated Conference on Software Development and Object Technologies. - Cham : Springer International Publishing , 2017 . - pp. 19-34
ISBN 978-3-319-46535-7
DOI: https://doi.org/10.1007/978-3-319-46535-7_2

Further data

Item Type: Article in a book
Refereed: Yes
Institutions of the University: Faculties > Faculty of Mathematics, Physics und Computer Science > Department of Mathematics > Lehrstuhl Wissenschaftliches Rechnen
Faculties > Faculty of Mathematics, Physics und Computer Science > Department of Mathematics > Lehrstuhl Wissenschaftliches Rechnen > CLehrstuhl Wissenschaftliches Rechnen - Univ.-Prof. Dr. Mario Bebendorf
Faculties > Faculty of Mathematics, Physics und Computer Science > Department of Mathematics >
Faculties > Faculty of Mathematics, Physics und Computer Science > Department of Mathematics > >
Research Institutions > Research Centres > Forschungszentrum für Modellbildung und Simulation (MODUS)
Research Institutions > Research Centres > Forschungszentrum für Wissenschaftliches Rechnen an der Universität Bayreuth - HPC-Forschungszentrum
Result of work at the UBT: No
DDC Subjects: 000 Computer Science, information, general works > 004 Computer science
500 Science > 510 Mathematics
500 Science > 550 Earth sciences, geology
Date Deposited: 24 Sep 2019 09:24
Last Modified: 24 Sep 2019 09:24
URI: https://eref.uni-bayreuth.de/id/eprint/52272