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Faster Switching with Less Overvoltage : Limitations in Current, Parasitics and Paralleled Chips

Title data

Rodriguez de Mora, Pablo ; Bakran, Mark-M.:
Faster Switching with Less Overvoltage : Limitations in Current, Parasitics and Paralleled Chips.
2021
Event: PCIM Europe digital days 2021 , 3-7 May 2021 .
(Conference item: Conference , Paper )

Official URL: Volltext

Abstract in another language

This paper explores the turn-off switching behavior of a 3rd. Gen. SiC-MOSFET at its maximum speed; that is, with zero external gate resistance. It is observed that the waveforms do not follow the typical trajectories and the device shows a mechanism that reduces the switching losses and the expected over-voltage. The behavior of a single chip is studied with the double pulse test, where the applicable area of this behavior is evaluated. The influence of chip parameter dispersion is analyzed as well as the influence of gate loop and DC-link parasitic inductance. Finally, the challenges of parallel switching are identified in simulation.

Further data

Item Type: Conference item (Paper)
Refereed: No
Institutions of the University: Faculties > Faculty of Engineering Science
Faculties > Faculty of Engineering Science > Chair Mechatronics
Profile Fields > Advanced Fields > Advanced Materials
Profile Fields > Emerging Fields > Energy Research and Energy Technology
Research Institutions > Affiliated Institutes > TechnologieAllianzOberfranken (TAO)
Result of work at the UBT: Yes
DDC Subjects: 600 Technology, medicine, applied sciences > 620 Engineering
Date Deposited: 08 Jul 2021 08:54
Last Modified: 08 Jul 2021 08:54
URI: https://eref.uni-bayreuth.de/id/eprint/65125