at Google ScholarTitle data
Keller, Jörg ; Rauber, Thomas ; Rederlechner, Bernd:
Scalability Analysis for Conservative Simulation of Logical Circuits.
In: VLSI Design.
Vol. 9
(1999)
Issue 3
.
- pp. 219-235.
ISSN 1065-514X
DOI: https://doi.org/10.1155/1999/14802
Further data
| Item Type: | Article in a journal |
|---|---|
| Refereed: | Yes |
| Institutions of the University: | Faculties > Faculty of Mathematics, Physics und Computer Science > Department of Computer Science > Chair Applied Computer Science II > Chair Applied Computer Science II - Univ.-Prof. Dr. Thomas Rauber Faculties Faculties > Faculty of Mathematics, Physics und Computer Science Faculties > Faculty of Mathematics, Physics und Computer Science > Department of Computer Science Faculties > Faculty of Mathematics, Physics und Computer Science > Department of Computer Science > Chair Applied Computer Science II |
| Result of work at the UBT: | No |
| DDC Subjects: | 000 Computer Science, information, general works > 004 Computer science |
| Date Deposited: | 11 Dec 2019 13:48 |
| Last Modified: | 11 Dec 2019 13:48 |
| URI: | https://eref.uni-bayreuth.de/id/eprint/25300 |