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Modelling parallel SiC MOSFETs : thermal selfstabilisation vs. switching imbalances

Title data

Bertelshofer, Teresa ; März, Andreas ; Bakran, Mark-M.:
Modelling parallel SiC MOSFETs : thermal selfstabilisation vs. switching imbalances.
In: IET Power Electronics. Vol. 12 (2019) Issue 5 . - pp. 1071-1078.
ISSN 1755-4535
DOI: https://doi.org/10.1049/iet-pel.2018.5418

Abstract in another language

This article presents a numerical method in combination with a device simulation model used to analyse the parallel
connection of several silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) dies. Parallel connection is necessary to achieve the desired current carrying capability of the main inverters for xEV-drives. With this method, the effect of asymmetries within the chips’ parameters, especially the gate threshold voltage, is investigated. The investigation results quantify to what extent the positive temperature coefficient of the on-state resistance can mitigate the overheating of one chip
caused by switching loss imbalance. The results are used to define the necessary derating of the inverter output power so that no single chip is thermally overstressed.

Further data

Item Type: Article in a journal
Refereed: Yes
Institutions of the University: Faculties > Faculty of Engineering Science > Chair Mechatronics > Chair Mechatronics - Univ.-Prof. Dr.-Ing. Mark-M. Bakran
Profile Fields > Advanced Fields > Advanced Materials
Profile Fields > Emerging Fields > Energy Research and Energy Technology
Research Institutions > Research Units > ZET - Zentrum für Energietechnik
Result of work at the UBT: Yes
DDC Subjects: 600 Technology, medicine, applied sciences > 620 Engineering
Date Deposited: 13 Jun 2019 07:14
Last Modified: 13 Jun 2019 07:14
URI: https://eref.uni-bayreuth.de/id/eprint/49483