Mitigating Drain Source Voltage Oscillation with Low Switching Losses for SiC Power MOSFETs Using FPGA-Controlled Active Gate Driver

Titelangaben

Li, Zheming ; Maier, Robert ; Bakran, Mark-M.:
Mitigating Drain Source Voltage Oscillation with Low Switching Losses for SiC Power MOSFETs Using FPGA-Controlled Active Gate Driver.
In: 2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe). - Piscataway, NJ : IEEE , 2020
ISBN 978-90-75815-36-8
DOI: https://doi.org/10.23919/EPE20ECCEEurope43536.2020.9215813

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Abstract

In order to improve the switching performance of SiC MOSFETs at turn-off, the drain-source voltage
oscillation should be mitigated with low switching losses. To achieve this improvement, an approach,
which uses an FPGA-controlled active gate driver with two level switchable gate resistances, is
investigated and presented in this paper. To ensure the performance of this approach for varying
operating points in a wide range, three methods are shown and compared to find the best solution.