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Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Title data

Reuben, John ; Pechmann, Stefan:
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Vol. 29 (1 April 2021) . - 14 S..
ISSN 1557-9999
DOI: https://doi.org/10.1109/TVLSI.2021.3068470

Official URL: Volltext

Abstract in another language

To overcome the "von Neumann bottleneck," methods to compute in memory are being researched in many emerging memory technologies, including resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/imply logic. In this work, we propose a method to implement a majority gate in a transistor-accessed ReRAM array during the READ operation. Together with not gate, which is also implemented in memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. While many methods have been proposed recently to implement the Boolean logic in memory, the latency of in-memory adders implemented as a sequence of such Boolean operations is exorbitant (O(n)). Parallel-prefix (PP) adders use prefix computation to accelerate addition in conventional CMOS-based adders. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is demonstrated how PP adders can be implemented in memory in O(log(n)) latency. The proposed in-memory addition technique incurs a latency of 4·log(n)+6 for n-bit addition and is energy-efficient due to the absence of sneak currents in 1Transistor-1Resistor configuration.

Further data

Item Type: Article in a journal
Refereed: Yes
Keywords: 1Transistor-1Resistor (1T-1R); compute-in-memory; in-memory computing; logic-in-memory; majority gate; majority logic; memristor; nonvolatile memory (NVM); parallel-prefix (PP) adder; processing-in-memory; readout circuit; resistive RAM (ReRAM); sense amplifier (SA); von Neumann bottleneck; Logic gates; Adders; Logic arrays; Resistance; Arrays; Resistive RAM; Transistors
Institutions of the University: Faculties > Faculty of Engineering Science > Chair Communication Electronics > Chair Communication Electronics - Univ.-Prof. Dr.-Ing. Amélie Marietta Hagelauer
Result of work at the UBT: Yes
DDC Subjects: 600 Technology, medicine, applied sciences > 620 Engineering
Date Deposited: 08 Apr 2021 07:11
Last Modified: 08 Apr 2021 07:11
URI: https://eref.uni-bayreuth.de/id/eprint/64615