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Experimental validation of a chip area optimized 3.3 kV SiC half bridge for HVDC converters

Title data

Bergmann, Lukas ; Wahle, Marcus ; Bakran, Mark-M.:
Experimental validation of a chip area optimized 3.3 kV SiC half bridge for HVDC converters.
2022
Event: APEC Applied Power Electronics Conference , 20.03.-24.03.2022 , Houston, Texas, USA.
(Conference item: Conference , Paper )

Abstract in another language

The content of this paper demonstrates the experimental validation of a semiconductor area optimized 3.3 kV SiC half bridge for HVDC converters. The core of this work is a comparison on submodule level between the conventional half bridge and the asymmetric HVDC specific half bridge, which features an asymmetrical semiconductor area between high side and low side switch. The main motivation of this approach is to save costly SiC semiconductor area and exploit the asymmetrical stress of low side and high side switches in the submodules of a Modular Multilevel Converter (MMC). The system level design is already published and therefore, only the basics it will be presented. The focus is on switching characteristics of the MOSFET and the freewheeling body diode. The impact of design methods on dead time optimization, switching overvoltage, reverse recovery behavior, current slope and switching losses is investigated.

Further data

Item Type: Conference item (Paper)
Refereed: Yes
Institutions of the University: Faculties > Faculty of Engineering Science > Chair Mechatronics > Chair Mechatronics - Univ.-Prof. Dr.-Ing. Mark-M. Bakran
Profile Fields > Advanced Fields > Advanced Materials
Profile Fields > Emerging Fields > Energy Research and Energy Technology
Research Institutions > Research Units > ZET - Zentrum für Energietechnik
Result of work at the UBT: Yes
DDC Subjects: 600 Technology, medicine, applied sciences > 620 Engineering
Date Deposited: 29 Jul 2022 06:37
Last Modified: 29 Jul 2022 06:46
URI: https://eref.uni-bayreuth.de/id/eprint/71260