Mitigating Drain Source Voltage Oscillation with Low Switching Losses for SiC Power MOSFETs Using FPGA-Controlled Active Gate Driver

Title data

Li, Zheming ; Maier, Robert ; Bakran, Mark-M.:
Mitigating Drain Source Voltage Oscillation with Low Switching Losses for SiC Power MOSFETs Using FPGA-Controlled Active Gate Driver.
In: 2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe). - Piscataway, NJ : IEEE , 2020
ISBN 9789075815368
DOI: https://doi.org/10.23919/EPE20ECCEEurope43536.2020.9215813

Official URL:

Abstract in another language

In order to improve the switching performance of SiC MOSFETs at turn-off, the drain-source voltage
oscillation should be mitigated with low switching losses. To achieve this improvement, an approach,
which uses an FPGA-controlled active gate driver with two level switchable gate resistances, is
investigated and presented in this paper. To ensure the performance of this approach for varying
operating points in a wide range, three methods are shown and compared to find the best solution.

Further data

Item Type:	Article in a book
Refereed:	No
Institutions of the University:	Faculties > Faculty of Engineering Science Faculties > Faculty of Engineering Science > Chair Mechatronics Faculties > Faculty of Engineering Science > Chair Mechatronics > Chair Mechatronics - Univ.-Prof. Dr.-Ing. Mark-M. Bakran Profile Fields > Advanced Fields > Advanced Materials Profile Fields > Emerging Fields > Energy Research and Energy Technology Research Institutions > Affiliated Institutes > TechnologieAllianzOberfranken (TAO) Faculties Profile Fields Profile Fields > Advanced Fields Profile Fields > Emerging Fields Research Institutions Research Institutions > Affiliated Institutes
Result of work at the UBT:	Yes
DDC Subjects:	600 Technology, medicine, applied sciences > 620 Engineering
Date Deposited:	19 Oct 2020 05:43
Last Modified:	05 Jun 2025 12:34
URI:	https://eref.uni-bayreuth.de/id/eprint/57255