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Derating of parallel SiC MOSFETs considering switching imbalances

Title data

Bertelshofer, Teresa ; März, Andreas ; Bakran, Mark-M.:
Derating of parallel SiC MOSFETs considering switching imbalances.
2018
Event: PCIM Europe 2018 , 05.-07.06.2018 , Nürnberg.
(Conference item: Conference , Paper )

Abstract in another language

This paper presents a numerical method used
to analyse the parallel connection of several SiC
MOSFET dies. Parallel connection is necessary to
achieve the desired current carrying capability of
main inverters for xEV-drives. With this method the
effect of asymmetries within the chips’ parameters,
especially the threshold voltage, are investigated.
The investigation results quantify to what extent the
PTC behaviour of the on-state resistance can mitigate
the overheating of one chip caused by switching
loss imbalance. The results are used to define
the necessary derating of the inverter output power,
so that no single chip is thermally overstressed.

Further data

Item Type: Conference item (Paper)
Refereed: Yes
Institutions of the University: Faculties > Faculty of Engineering Science > Chair Mechatronics > Chair Mechatronics - Univ.-Prof. Dr.-Ing. Mark-M. Bakran
Profile Fields > Advanced Fields > Advanced Materials
Profile Fields > Emerging Fields > Energy Research and Energy Technology
Research Institutions > Research Units > ZET - Zentrum für Energietechnik
Faculties
Faculties > Faculty of Engineering Science
Faculties > Faculty of Engineering Science > Chair Mechatronics
Profile Fields
Profile Fields > Advanced Fields
Profile Fields > Emerging Fields
Research Institutions
Research Institutions > Research Units
Result of work at the UBT: Yes
DDC Subjects: 600 Technology, medicine, applied sciences > 620 Engineering
Date Deposited: 13 Nov 2018 09:36
Last Modified: 13 Nov 2018 09:36
URI: https://eref.uni-bayreuth.de/id/eprint/46303