Titlebar

Export bibliographic data
Literature by the same author
plus on the publication server
plus at Google Scholar

 

Optimization of the chip area in 3.3 kV SiC submodules for HVDC converters

Title data

Bergmann, Lukas ; Wahle, Marcus ; Bakran, Mark-M.:
Optimization of the chip area in 3.3 kV SiC submodules for HVDC converters.
2021
Event: 23rd European Conference on Power Electronics and Applications (EPE'21 ECCE Europe) , 06.-10. Sept. 2021 , Virtual.
(Conference item: Conference , Paper )

Abstract in another language

The content of this paper describes the optimizing of the semiconductor area in HV-SiC MOSFET based
MMC HB submodules. This paper propose a design method of reducing the semiconductor area due to
the asymmetric arm current in a MMC. The mathematical derivation of the design rule and loss
performance compared to the conventional Si HB and SiC HB is presented. A power loss simulation on
submodule level shows the final results of power losses, junction temperatures of the components and
the overall efficiency at different DC converter currents and AC load angles. The increase of the area
specific power capability of all three types of semiconductor device modules in the application of a
MMC submodule proves the economical benefit of an optimized HVDC SiC HB.

Further data

Item Type: Conference item (Paper)
Refereed: Yes
Additional notes: ISBN 978-9-0758-1537-5
Institutions of the University: Faculties > Faculty of Engineering Science > Chair Mechatronics > Chair Mechatronics - Univ.-Prof. Dr.-Ing. Mark-M. Bakran
Profile Fields > Advanced Fields > Advanced Materials
Profile Fields > Emerging Fields > Energy Research and Energy Technology
Research Institutions > Research Units > ZET - Zentrum für Energietechnik
Result of work at the UBT: Yes
DDC Subjects: 600 Technology, medicine, applied sciences > 620 Engineering
Date Deposited: 22 Feb 2022 08:36
Last Modified: 22 Feb 2022 08:36
URI: https://eref.uni-bayreuth.de/id/eprint/68721