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Bergmann, Lukas ; Wahle, Marcus ; Bakran, Mark-M.:
Optimization of the chip area in 3.3 kV SiC submodules for HVDC converters.
2021
Veranstaltung: 23rd European Conference on Power Electronics and Applications (EPE'21 ECCE Europe)
, 06.-10. Sept. 2021
, Virtual.
(Veranstaltungsbeitrag: Kongress/Konferenz/Symposium/Tagung
,
Paper
)
Abstract
The content of this paper describes the optimizing of the semiconductor area in HV-SiC MOSFET based
MMC HB submodules. This paper propose a design method of reducing the semiconductor area due to
the asymmetric arm current in a MMC. The mathematical derivation of the design rule and loss
performance compared to the conventional Si HB and SiC HB is presented. A power loss simulation on
submodule level shows the final results of power losses, junction temperatures of the components and
the overall efficiency at different DC converter currents and AC load angles. The increase of the area
specific power capability of all three types of semiconductor device modules in the application of a
MMC submodule proves the economical benefit of an optimized HVDC SiC HB.