at Google ScholarTitle data
Hofstetter, Patrick ; Maier, Robert ; Bakran, Mark-M.:
Influence of the Threshold Voltage Hysteresis and the Drain Induced Barrier Lowering on the Dynamic Transfer Characteristic of SiC Power MOSFETs.
2019
Event: APEC 2019
, 17.03.-21.03.2019
, Anaheim, USA.
(Conference item: Conference
,
Paper
)
Abstract in another language
This paper focuses on dynamic transfer characteristics of SiC MOSFETs, which are derived from the actual switching operation and are different from the usual static characteristics. A new approach to measure the parasitic common source elements is shown, using a non-harmful short circuit pulse. This is important for the correction of the measured gate source voltage, especially in packages without Kelvin source. The resulting transfer characteristics show the threshold voltage hysteresis of SiC MOSFETs and additionally the interaction with the drain induced barrier lowering (DIBL) effect. Finally, the effect of different off-state times on the transfer characteristics and the turn-on process is shown.
Further data
| Item Type: | Conference item (Paper) |
|---|---|
| Refereed: | Yes |
| Institutions of the University: | Faculties > Faculty of Engineering Science > Chair Mechatronics > Chair Mechatronics - Univ.-Prof. Dr.-Ing. Mark-M. Bakran Profile Fields > Advanced Fields > Advanced Materials Profile Fields > Emerging Fields > Energy Research and Energy Technology Research Institutions > Research Units > ZET - Zentrum für Energietechnik Faculties Faculties > Faculty of Engineering Science Faculties > Faculty of Engineering Science > Chair Mechatronics Profile Fields Profile Fields > Advanced Fields Profile Fields > Emerging Fields Research Institutions Research Institutions > Research Units |
| Result of work at the UBT: | Yes |
| DDC Subjects: | 600 Technology, medicine, applied sciences > 620 Engineering |
| Date Deposited: | 13 Jun 2019 07:01 |
| Last Modified: | 13 Jun 2019 07:01 |
| URI: | https://eref.uni-bayreuth.de/id/eprint/49480 |